Memory built-in self testing (memory BIST) often relies on the IEEE1149.1 standard to test and diagnose memories. This approach involves the existence of a16-state state machine, which may be referred to as a Joint Test Action Group (JTAG) Macro. The IEEE1149.1 standard also involves four or five Test Access Ports (TAP) to be present in the design. Although it provides a number of benefits in terms of testing and diagnosing a chip, JTAG approaches can increase the chip cost in terms of hardware and extra ports. Moreover, JTAG approaches may add unnecessary hardware.
For memory testing without JTAG, scripts may be provided to draw all the required memory BIST engine inputs to a top-level design. It may then be the responsibility of a third party tool to understand this and generate patterns accordingly. Such a script method can lead to numerous unwanted pins on a chip design which may be a concern because designs can be constrained by number of pins. Script approaches may also require a user to manually insert glue logic to control the multiple memory BIST engines from few top-level pins. As a result, the designer may be forced to write the patterns manually.